参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 55/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Getting Started
Simulate the
This section describes the following simulation techniques:
Example Design
■
■
Simulate with IP Functional Simulation Models
You can simulate the example design using the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.
f
You can use the IP functional simulation model with any
Altera-supported VHDL or Verilog HDL simulator. To simulate the
example design with the ModelSim ? simulator, follow these steps:
1.
Obtain a memory model that matches your chosen parameters and
save it to the < directory name > testbench directory. For example,
you can download a RLDRAM II model from the Micron web site at
www.micron.com .
1
Before running the simulation you may also need to edit the
testbench to match the chosen RLDRAM II model.
2.
3.
4.
Start the ModelSim-Altera simulator.
Change your working directory to your IP Toolbench-generated file
directory < directory name > testbench\modelsim.
To simulate with an IP functional simulation model simulation, type
the following command:
source <variation name> _vsim.tcl r
1
Before running the simulation, you may have to edit the
set memory model parameter in the <variation
name> _vsim.tcl file to match the selected RLDRAM II
model.
Altera Corporation
November 2009
5.
For a gate-level timing simulation (VHDL or Verilog HDL
ModelSim output from the Quartus II software), type the following
commands:
set use_gate_model 1 r
MegaCore Version 9.1 3–11
RLDRAM II Controller MegaCore Function User Guide
相关PDF资料 |
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|---|---|
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| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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