参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 16/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
Block Description
Pipeline Registers
IP Toolbench can insert pipeline registers into the datapath to help meet
timing at higher frequencies. IP Toolbench offers the following pipeline
options:
■
■
Insert address and command and write data pipeline registers. The
pipeline depth is the same for the write-data path and the address
and command path. The write data and address and command
pipeline registers are clocked off the system clock.
Insert read data and QVLD pipeline registers. The pipeline depth is
the same for the read-data path and the QVLD path. The read data
and QVLD pipeline registers are clocked off the clock that captures
the read data—the delayed rldramii_qk[] signal in DQS mode;
the external capture clock in non-DQS mode.
DQS Group
The datapath instantiates one or more DQS groups, which generates
write data, rldramii_dq[] (CIO devices), or rldramii_d[] (SIO
devices) and captures read data rldramii_dq[] (CIO devices), or
rldramii_q[] (SIO devices). The IP Toolbench DQ per DQS (CIO
devices) or Q per DQS (SIO devices) parameter determines the DQS
group width. For example, if DQ per DQS is 9 bits, the
control_wdata[] and control_rdata[] signals are 18-bits wide. To
build larger widths, the datapath instantiates multiple DQS group
modules to increase the data-bus width in increments of DQ per DQS (or
Q per DQS ) bits.
1
1
The datapath generates the DM output, rldramii_dm[] , in the
DM group module. It generates the DM output in the same way
as the write data.
The datapath captures the QVLD input, rldramii_qvld[] , in
the QVLD group module. The rldramii_qvld[] signal is
captured in the same way that the DQS group module captures
the read data. In DQS mode, the delayed rldramii_qk[]
captures rldramii_qvld[] ; in non-DQS mode, the external
clock captures rldramii_qvld[] .
devices DQS group block diagram (DQS mode, CIO devices).
2–6 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。