参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 27/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Figure 2–11. RLDRAM II Initialization Sequence
rldramii_clk
Command
MRS
MRS
RF0
RF1
RF7
AC
rldramii_a[]
0
0 CFG
Ax
rldramii_ b a[ ]
200 m s
10 Clock
0
2,04 8
1
6 x 2,04 8
7
Bx
Minim u m
Cycles
t MRSC
Clock Cycles
Clock Cycles
t RC
MRS = Mode Register Set
CFG = Mode Register Config u ration Data
RFx = Refresh
AC = User Command
The mode register set (MRS) command configures the RLDRAM II
devices. In the ten-cycle MRS sequence, the first nine MRS commands are
dummy commands and all address bits are held at zero, to reset the
RLDRAM II DLL; the final MRS command configures the memory. The
RLDRAM II configuration data (CFG) is output on the
rldramii_a_0[] bus during the final MRS command. The following
memory parameters are setup during the final MRS command cycle:
■
■
■
■
RLDRAM II termination
Impedance matching resistor
DLL enable/disable
RLDRAM II configuration
Writes
When you assert local_write_req , the control logic issues the write
transaction immediately at the memory interface. The control logic then
requests write data by asserting local_wdata_req , so that the
RLDRAM II t WL period is satisfied during write transactions. This
functionality means that the write request is decoupled from the write
data.
interface. In this example, the memory burst length is set to eight beats.
The RLDRAM II device is setup with a t RC of six-clock cycles
(configuration two).
Altera Corporation
November 2009
MegaCore Version 9.1 2–17
RLDRAM II Controller MegaCore Function User Guide
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