参数资料
型号: IP-RLDRAMII
厂商: Altera
文件页数: 61/62页
文件大小: 0K
描述: IP RLDRAM II CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: RLDRAM II 控制器
许可证: 初始许可证
Additional Information
Revision History
The table below displays the revision history for the chapters in this user
guide.
Date
November 2009
March 2009
November 2008
Version
9.1
9.0
8.1
Updated the release information.
Updated the release information.
Updated the release information.
Changes Made
May 2008
8.0
Added timing assignment information for capture to first level resyncronization
registers
Registers clocked by DQS in the core now use undelayed DQS
May 2007
March 2007
7.1
7.0
No changes.
No changes.
December 2006
6.1
Added timing assignment information for 18 and 36-bit RLDRAM II devices
Updated device initialization sequence
April 2006
October 2005
1.1.0
1.0.0
Updated format.
First published.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the
following table.
Information Type
Technical support
Technical training
Technical training services
Product literature
FTP site
Note to table:
Contact Note (1)
Altera Corporation
(1)
You can also contact your local Altera sales office or sales representative.
MegaCore Version 9.1 i
RLDRAM II Controller MegaCore Function User Guide
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