参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 53/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Getting Started
project directory. The names and types of files specified in the IP
Toolbench report vary based on whether you created your design with
VHDL or Verilog HDL
Table 3–1. Generated Files (Part 1 of 2) Note (1) , (2) , (3)
Filename
< variation name >. vhd , or .v
< variation name > .cmp
< variation name > .bsf
< variation name > .sdc
altera_vhdl_support.vhd
< variation name > _example_driver.vhd or .v
<top-level name> .vhd or .v
add_constraints_for_ <variation name> .tcl
rldramii_pll_ <device name> .vhd or .v
rldramii_fbpll_ <device name> .vhd or .v
< variation
name > _auk_rldramii_addr_cmd_reg.vhd or .v
< variation name > _auk_rldramii_clk_gen.vhd or .v
< variation
name > _auk_rldramii_controller_ipfs_wrapper.vh
d or .v
< variation
Description
A MegaCore function variation file, which defines a
VHDL or Verilog HDL description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
A VHDL component declaration file for the MegaCore
function variation. Add the contents of this file to any
VHDL architecture that instantiates the MegaCore
function.
Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
A Synopsys Design Constraints (SDC) file. Use this SDC
file with the DDR timing wizard (DTW)-generated SDC
file when using TimeQuest. You must copy the contents
of this file into the DTW-generated SDC file, so the
example design has the correct timing constraints when
using TimeQuest.
A VHDL package that contains functions for the
generated entities. This file may be shared between
MegaCore functions.
Example driver.
Example design file.
Add constraints script.
System PLL.
Fedback PLL.
Address and command output registers.
Memory clock generator.
A file that instantiates the controller.
VHDL or Verilog HDL IP functional simulation model.
name > _auk_rldramii_controller_ipfs_wrapper.vh
o or .vo
< variation name > _auk_rldramii_datapath.vhd or .v Datapath.
Altera Corporation
November 2009
MegaCore Version 9.1 3–9
RLDRAM II Controller MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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