参数资料
型号: IP-RLDRAMII
厂商: Altera
文件页数: 42/62页
文件大小: 0K
描述: IP RLDRAM II CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: RLDRAM II 控制器
许可证: 初始许可证
Parameters
Table 2–12 shows the pin loading parameters.
Table 2–12. Pin Loading Parameters
Parameter
Pin loading on FPGA
DQ/DQS pins
Pin loading on FPGA
address and
command pins
Pin loading on FPGA
Range (pF)
0 to 100
0 to 100
0 to 100
Description
Enter the pin loading to match your board and memory devices.
Enter the pin loading to match your board and memory devices.
Enter the pin loading to match your board and memory devices.
clock pins
Project Settings
Table 2–13 shows the example design settings.
Table 2–13. Example Design Settings
Parameter
Automatically apply
RLDRAM II controller-
Description
When this option is turned on, the next time you compile, the Quartus II software
automatically runs the add constraints script. Turn off this option if you do not want
specific constraints to the the script to run automatically.
Quartus II project
Update the example
design file that
instantiates the RLDRAM
II controller variation
Update example design
system PLL
When this option is turned on, IP Toolbench parses and updates the example design
file. It only updates sections that are between the following markers:
<<START MEGAWIZARD INSERT <tagname>
<<END MEGAWIZARD INSERT <tagname>
If you edit the example design file, ensure that your changes are outside of the
markers or remove the markers. Once you remove the markers, you must keep the
file updated, because IP Toolbench can no longer update the file.
When this option is turned on, IP Toolbench automatically overwrites the PLL.Turn off
this option, if you do not want the wizard to overwrite the PLL.
2–32 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
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