参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 39/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Memory
Table 2–7. Memory Type Parameters
Parameter
RLDRAM II device
Range
Part number
–
Units
Description
A part number for a particular memory device. Choosing
an entry sets many of the parameters in the wizard to the
correct value for the specified part. You can add your own
devices to this list by editing the memory_types.dat file in
the \constraints directory.
Clock speed
100 to 400
MHz
The memory controller clock frequency.The constraints
script and the datapath use this clock speed. It must be set
to the value that you intend to use. The first time you use
IP Toolbench or if you turn on Update example design
system PLL , it uses this value for the IP Toolbench-
generated PLL’s input and output clocks.
Interface voltage
DQ per DQS
Q per DQS
Data-bus width
1.5 or 1.8
8, 9, 16, 18
8, 9, 16, 18
Device
V
Bits
Bits
Bits
The RLDRAM II interface voltage.
Number of DQ bits per DQS input pin. CIO devices only.
Number of Q bits per DQS input pin. SIO devices only.
The width of the memory interface.
dependent
For more information about supported interface data
widths, refer to AN 325: Interfacing RLDRAM II with Stratix
II, Stratix & Stratix GX Devices .
Table 2–8. Memory Initialization Options
Parameter
Range
Description
Memory configuration 1, 2, or 3.
Refer to your RLDRAM II data sheet.
Burst length
Manually enter
initialization clock
cycles
Number of
initialization clock
cycles
Enable on-die
termination
Altera Corporation
November 2009
2, 4, or 8
On or off
16 to 80,000
On or off
Number of beats in the burst at the memory interface. The number of
beats at the local interface is half this value.
The wizard takes the number of initialization clock cycles from the
memory.dat file in the constraints directory. The number is
calculated from the initialization entry time and the clock speed. You
can manually enter a number for the initialization clock cycles if you
turn on Manually enter initialization clock cycles .
Refer to your RLDRAM II data sheet.
MegaCore Version 9.1 2–29
RLDRAM II Controller MegaCore Function User Guide
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