参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 41/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Timing
Table 2–10. Pipeline Options
Parameter
Number of address
and command and
write data pipeline
registers
Number of read data
pipeline registers
Range
0, 1, 2 or 3
0, 1, 2 or 3
Description
When you choose 1, 2, or 3 the wizard inserts 1, 2, or 3 pipeline
registers between the memory controller and the command and
address output registers and the write data output registers. These
registers may help to achieve the required performance at higher
frequencies.
When you choose 1, 2, or 3 the wizard inserts 1, 2, or 3 pipeline
registers between the read capture registers and the memory
controller. These registers may help to achieve the required
performance at higher frequencies.
Table 2–11. Clocking Modes
Parameter
Address and
command clock
Address and
command clock edge
Dedicated address
and command clock
PLL phase offset
Enable DQS mode
Use migratable byte
groups
Fedback PLL phase
offset
Altera Corporation
November 2009
Range
System, write,
or dedicated
Falling or rising
± 180 ?
On or off
On or off
± 180 ?
Description
The clock for the address and command output registers. For
system_clk choose System ; for write_clk , choose Write , and
for a separate clock, choose Dedicated .
If you choose Dedicated for the clock, ensure the clock phase allows
the Quartus II software to meet the setup time on the address and
command output registers.
The clock edge on which the addresses and commands are output.
Sets the dedicated address and command clock PLL phase for better
timing.
Turn on for DQS mode; otherwise the controller is in non-DQS mode
(Stratix II and Stratix II GX devices only). HardCopy II devices allow
DQS mode only.
When turned on, you can migrate the design to a migration device.
When turned off the wizard allows much greater flexibility in the
placement of byte groups. You can only turn on this option when
Enable DQS mode is turned off.
Sets the fedback clock PLL phase for read capture (non-DQS mode
only).
MegaCore Version 9.1 2–31
RLDRAM II Controller MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
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