参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 38/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
Parameters
Table 2–6. Datapath Interface Signals
Name
control_a[]
control_ba[]
control_cs_n
control_dm[]
Width
(Bits)
local_addr[]
3
1
The number of
RLDRAM II devices
Direction
Input
Input
Input
Input
Description
Address bits.
Bank address bits.
Chip select signal.
The DM bus, which has valid data in the same clock
cycles that control_wdata_valid is asserted.
attached to the
memory interface ×
2
control_doing_wr 1
Input
Control_doing_wr is asserted when the
controller is writing to the RLDRAM II devices and
controls the output enables on rldramii_dq[] or
rldramii_d[] .
control_ref_n
control_wdata[]
1
Data-bus width × 2
Input
Input
Refresh signal.
The write data bus, which has valid data in the same
clock cycles that control_wdata_valid is
asserted.
control_wdata_
valid
1
Input
Enables the write data bus and DM enable registers
so that they are only updated when valid data and
enables are available.
control_we_n
control_qvld[]
1
The number of
RLDRAM II devices
attached to the
memory interface
Input
Output
Write enable signal.
The read data valid flag.There is only one QVLD flag
per RLDRAM II device. The control_qvld[]
signal is aligned with the valid control_rdata[]
and is asserted during this period. The
control_qvld[] signal has the same
functionality as local_rdata_valid[] .
control_rdata[]
Data-bus width × 2
Output
The captured read data (same as
local_rdata[] ).
Parameters
2–28 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。