参数资料
型号: LXT6251A
英文描述: ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC
中文描述: 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料
文件页数: 17/76页
文件大小: 995K
代理商: LXT6251A
21 E1 SDH Mapper
LXT6251A
Datasheet
17
3.2.1
Receive Alarms
There are two alarms associated with the Telecom bus interface.
3.2.1.1
Parity Alarm
The receive telecom bus data integrity is monitored with a single odd parity bit. The parity is
calculated over the DTBDATA bus only. The mapper checks the parity for errors every 500mS
multiframe and indicates an alarm in
GLOB_INTS
Global Interrupt Source (00CH)
on page 60
if there are more than 16 errors within the 500mS time window. The interrupt is maskable in
INT_CONF
Interrupt Configuration Register (00BH)
on page 59
.
3.2.1.2
Loss of Multiframe
A loss of multiframe alarm is detected if the DTBH4EN signal is always low. The alarm status and
interrupt is indicated in
GLOB_INTS
Global Interrupt Source (00CH)
on page 60
.
Consequent Actions:
An LOM alarm will cause the SF alarm bit on the SAP bus to be high for all 21 tributaries. The
SF alarm is used to indicate errors that should cause a VC path protection event. The SAP bus
is described in detail in
Serial/Remote Alarm Processing Port
on page 40
.
Figure 3. LXT6251A Block Diagram
FIFO
MTD<1:21>
Lower order Path
Adaption
DTD<1:21>
DTC<1:21>
DTBDATA<7:0>
MTBDATA<7:0>
MTBPAR
MTBPAYEN
MTBH4EN
Serial
Alarm
Processing
A<8:0>
DSAPCLK
DSPAFRM
S/P
LPA
MTC<1:21>
Lower order Path
Termination
VC-12
POH
LPT
Unequipped
Generator
TU Pointer
Generation
LUG
HPA
Desynchronizer
& FIFO
Lower order Path Adaption
P/S
LPA
Low order
Connection
Supervision
Higher order
Path Adaption
Lower order Path Termination
and Overhead Monitor
VC-12
POH
LPT/LPOM
TU Pointer
Processing
HPA
Higher order Path
Adaption
CS
WR/RW
RD/E
DSAPDATA
MTBTUGEN
DTBYCK
DTBJ0J1EN
DTBPAYEN
DTBTUGEN
DTBH4EN
DTBPAR
Remote
Alarm
Processing
MRAPCLK
MRAPFRM
MRAPDATA
DATA<7:0>
MCUTYPE
AS
INT
STMMODE
OEN
RST
MTBJ0J1EN
PTSOH
PTTUGA
PTTUGB
ADM
Control
Timing Control
Synchronous Equipment Management Function (SEMF) Interface
Alarm & Control Memory
MTBDOE
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