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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 26/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
26
Datasheet
4.0
Transmit Section, Terminal Mode
At the MTDx/MTCx input pins, the Mapper expects to receive asynchronous E1 signals in the
form of NRZ data and clock. The mapper also requires the Telecom Bus timing signals
MTBJ0J1EN, MTBPAYEN, MTBH4EN, and MTBTUGEN (STM-1 only) to drive the internal
timing machine. Refer to
“
Telecom Bus Interface
”
on page 35
for details on these timing signals.
The E1 signal must be valid and within frequency tolerance. Should there be a Loss of Signal alarm
on an E1 input to the line interface circuits prior to the LXT6251A, it is the responsibility of the
LIU or other external element to generate a valid E1 clock and AIS signal. The LXT6251A does
not support a method to generate a mapped E1 AIS signal.
4.1
Low Order Path Adaptation
The E1 data and clock pairs immediately enter the first-in first-out memory within the lower order
path adaptation (LPA) block. The LPA block receives timing information from the master timing
control block to identify the frame positions of the Information (I) bytes, the stuffing indicators
C1C2, and the stuffing bits S1 and S2. This timing, along with the depth of the FIFO is used to
determine the stuffing decisions for each multiframe. The data out of the FIFO is converted to
parallel bytes at each I byte position, and the appropriate stuffing indicators and stuffing bits added
during the appropriate time slots. The output of the LPA block thus consists of a C12 container,
which includes I bytes, R bytes, and stuffing indicator bytes also containing four O bits. The
LXT6251A sets both the R bytes and the O bits to
‘
0
’
.
4.2
Low Order Path Termination
Next the LPT function adds the path overhead bytes V5, J2, N2, and K4. The following
descriptions detail the POH bytes and the supported bits within each byte.
4.2.1
V5 Processing
4.2.1.1
BIP-2
As the LPT block is generating the VC-12, a 2 bit Bit Interleave Parity (BIP-2) value is being
calculated on all the bytes. At the end of the multiframe, the BIP-2 value is inserted into the
following V5 byte (see Figure 4).
To aid the system designer in the testing phase, the LXT6251A includes a BIP error generator that
is enabled by setting the BipInv bit in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on
page 58
. The default value is
‘
0
’
, and the BIP value is not affected. When set to
‘
1
’
, the calculated
BIP value will be inverted on every V5 byte, simulating a degraded VC-12 for a receiver.
4.2.1.2
REI Bit
The Remote Error Indication bit is updated every multiframe by monitoring the receive side status
data on the Remote Alarm Port (RAP). The RAP port is further described in
“
Serial/Remote Alarm
Processing Port
”
on page 40
. If the corresponding receive side TU-12 tributary detects BIP-2
errors, the RAP port will indicate to the transmit LPT block that the REI bit should be set to
‘
1
’
.
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