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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 34/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
34
Datasheet
6.0
Application Information
6.1
Port Mapping Configuration
To allow for the design of a cost-reduced ADM mapper module, the LXT6251A supports a
programmable E1 port mapping feature that allows each E1 I/O port to be assigned to any tributary
time slot. The cost-reduced module may contain only four or eight E1 line interface circuits, but the
use of the Port Mapping would allow access to any TU-12 tributary within a TUG-3 or STM-0
payload at an ADM site.
There is a 5 bit Port Mapping register per tributary circuit that is used to configure the time slot on
which the circuit operates. Each of the 21 circuits has associated with it a set of alarm and control
registers (address range
x
0H through
x
FH) and the E1 I/O ports MTD(T)/MTC(T) and DTB(T)/
DTC(T), where T ranges from 1 to 21. By configuring the port mapping register to a timeslot, all
processing of the assigned TU-12 is performed by the hardware circuit associated with the port
mapping register. That is, when the Port Mapping function is used, both the register address and the
physical E1 port (both Tx and Rx) will operate on the selected TU-12 time slot.
Table 7
contains the default register values and the ITU specified Time Slot numbering for the 21
tributaries. In the STM-1 configuration, the input DTBTUGEN control pin determines the TUG-3
number (K). The default associations map port 1 to the first TU-12 time slot (1,1) and linearly
progress to port 21 with TU-12 slot 21 (7,3).
When configuring the port mapping registers, care must be taken to keep the value in each register
unique. If port 1 is assigned TS (2,1), then no other port should be assigned to this timeslot. Failure
to ensure this could result in an unstable system. It is also suggested that the multiplexer Telecom
bus be placed in tri-state (the TBTristate bit in the Global Configuration register) whenever the Port
Mapping registers are changed.
Table 7. E1 Port Time Slot Assignment
Tributary Circuit (Port)
Register Address
Default Value
Default
Time Slot
TU-12 Address (L, M)
1
161h
1
1
(1, 1)
2
162h
2
2
(2, 1)
3
163h
3
3
(3, 1)
4
164h
4
4
(4, 1)
5
165h
5
5
(5, 1)
6
166h
6
6
(6, 1)
7
167h
7
7
(7, 1)
8
168h
8
8
(1, 2)
9
169h
9
9
(2, 2)
10
16Ah
10
10
(3, 2)
11
16Bh
11
11
(4, 2)
12
16Ch
12
12
(5, 2)
13
16Dh
13
13
(6, 2)
14
16Eh
14
14
(7, 2)
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