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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 54/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
54
Datasheet
Default
When the LXT6251A is reset, it sets its
registers to predetermined default states. The
default state represents the minimum
functionality feature set required to
successfully bring up the system. Hence, it
does not represent the optimal system
configuration. It is the responsibility of
software to properly determine the operating
parameters, and optional system features
that are applicable, and to program the
LXT6251A registers accordingly.
Default = X
Undefined
Tributary
Register
Addressing
The first nibble of the tributary register
address (address bits <3:0>) represents a
specific register in a given tributary. The
upper 5 bits of the address (bits <8:4>)
identify the tributary and is represented by
the letter
‘x’
. For example,
x
CH refers to the
CH register in tributary
x
. The
x
is the
Tributary identifier with valid values of 1H to
15H (1 to 21 decimal). Thus, 14AH refers to
tributary 20
’
s K4 Status Register.
Table 17. Register Address Map
Address
Mnemonic
Register Name
Type
Page #
Global Configuration Registers
000H
GLOB_CONF
Global Configuration
R/W
page 55
001
–
003H
TADD_CONF
Transmit Address Configuration
R/W
page 56
008H
J2_MRST
J2 Memory Reset
WO
page 57
005
–
009H
—
Reserved
—
00AH
CHIP_ID
Chip Identification
RO
page 59
00BH
INT_CONF
Interrupt Configuration
R/W
page 59
00CH
GLOB_INTS
Global Interrupt Source
RO
page 60
00D
–
00FH
TRIB_ISRC
Tributary Interrupt Source Identification
RO
page 60
TU Tributary Registers
(
x
=1
–
15H and represents each of the 21 tributary register sets)
x
0
–
x
1H
TRIB_INT
Tributary Interrupt
RO
page 61
x
2
–
x
3H
TRIB_STA
Tributary Status
RO
page 63
x
4
–
x
5H
TRIB_INTE
Tributary Interrupt Enable
R/W
page 62
x
6
–
x
7H
BIP2_ERRCNT
BIP2 Error Counter
RO
page 63
x
8
–
x
9H
REI_CNT
Remote Error Indication Counter
RO
page 64
x
AH
K4_STA
K4 Status
RO
page 64
x
BH
V5_STA
V5 Status
RO
page 64
x
CH
J2_ESDATA
J2 Expected String Data
R/W
page 58
x
DH
ERRI_CONF
Error Insert Configuration
R/W
page 58
x
EH
SIGLA_SET
Signal Label Set
R/W
page 57
x
FH
J2_TSDATA
J2 Transmit String Data
R/W
page 58
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