- 您现在的位置：买卖IC网 > PDF目录369885 > LXT6251A ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC PDF资料下载
参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 64/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页当前第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
LXT6251A
—
21 E1 SDH Mapper
64
Datasheet
This counter increments each time a BIP error event in the Low Order Path section is detected. To
access the count, the microprocessor must provide a Write command to the MSB address bit of
register x6H at least 3 byte clock periods (0.5us in STM-0) before the two Read commands. The
Write command clears the counter after buffering it.
8.6.3
REI_CNT
—
Remote Error Indication (REI) Counter (
x
9
–
x
8H)
x
=1
–
15H;
x
9H=Bits<15:8>,
x
8H=Bits<7:0> (Byte access only)
This counter increments each frame in which the receive V5 REI bit is set. To access the count, the
microprocessor must provide a Write command to the MSB address bit of register x9H at least
three byte clock periods (0.5us in STM-0) before the two Read commands. The Write command
clears the counter after buffering it.
8.6.4
K4_STA
—
K4 Status (
x
AH)
x
=1
–
15H
The K4 byte provides an Enhanced RDI that can be retrieved via a read of this register. This
register is updated only if there is a change in the V5 RDI bit and the tributary source supports K4
ERDI.
8.6.5
V5_STA
—
V5 Status Register (
x
BH)
x
=1
–
15H
The V5 status register is provided for raw access to the received V5 byte (see Figure 4). There is no
alarm or INT generation directly associated with this register. The value in this register changes
every multiframe (500uS).
Bit
Name
Description
Type
Default
15:12
Reserved
Unused
11:0
BipCnt
Bits<11:8> are the most significant byte of the BIP error event counter.
Bits<7:0> are the least significant bits.
RO
X
Bit
Name
Description
Type
Default
15:11
Reserved
Unused
10:0
LptReiCnt
Bits<10:8> are the most significant bits of the Low Order Path
OverHead REI error event counter. Bits<7:0> are the least significant
bits.
RO
X
Bit
Name
Description
Type
Default
7:4
Reserved
RO
0
3:1
Enhanced RDI
K4 ERDI bits.
RO
X
0
Reserved
RO
0
相关PDF资料 |
PDF描述 |
|---|---|
| LXT903PC | LAN Transceiver |
| LXT905LC | Laser Mouse VCSEL Assembly Clip |
| LXT905LE | Single-Mode Vertical-Cavity Surface Emitting laser (VCSEL) |
| LXT905PC | LAN TRANSCEIVER|SINGLE|CMOS|LDCC|28PIN|PLASTIC |
| LXT905PE | LAN TRANSCEIVER|SINGLE|CMOS|LDCC|28PIN|PLASTIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LXT901 | 制造商:LVL1 制造商全称:LVL1 功能描述:8QLYHUVDO (WKHUQHW 7UDQVFHLYHU |
| LXT901/LXT907 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LXT901. LXT907 - Design Guide for LXT901/907 Ethernet Interface Connection to Motorola MC68EN360 Controller |
| LXT901A | 制造商:LVL1 制造商全称:LVL1 功能描述:8QLYHUVDO (WKHUQHW 7UDQVFHLYHU |
| LXT901ALC | 制造商:LEVEL ONE 功能描述: |
| LXT901ALE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LAN Transceiver |
发布紧急采购，3分钟左右您将得到回复。