21 E1 SDH Mapper
—
LXT6251A
Datasheet
23
3.4.2.3
Trace Identifier Mismatch
The chip compares the received J2 string with the one stored in memory. If the calculated CRC-7
matches that of the received value, but there are errors in the comparison of the remaining 15 bytes,
the TIM status bit is set in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
. There is no
filtering of this alarm, since the CRC-7 match will indicate the J2 word has been received without
error. The TIM status bit is cleared when the J2 string is received without errors.
Whenever the TIM status bit changes the TIM interrupt bit in
“
TRIB_INT
—
Tributary Interrupt
(x1
–
x0H)
”
on page 61
is set.
Consequent Actions:
An RDI Indication will be sent to the transmitter via the SAP interface
Outgoing E1 data toward the PDH network will be forced to AIS with derived 2.048MHz
clock
3.4.3
N2 Processing
N2 processing is not implemented at this time.
3.4.4
K4 Processing
The K4 byte contains a protection function and an Enhanced RDI (ERDI) function. The
LXT6251A supports the ERDI function. No alarms or interrupts will be generated based only on
the K4 ERDI information The V5 RDI bit generates the alarms.
3.4.4.1
Enhanced RDI
Upon detection of a V5 RDI alarm,
“
K4_STA
—
K4 Status (xAH)
”
on page 64
can be accessed to
determine the nature of the RDI alarm, assuming the trail termination source supports the K4 ERDI
processing. The following defects are supported in the ERDI
3.4.5
Summary of Alarms causing E1 AIS
A number of alarms cause the LXT6251A to generate an all 1
’
s AIS signal at the E1 output port.
The following list summarizes those alarm and the conditions.
Table 4. Enhanced RDI Interpretation
K4, bit 5
K4, bit 6
K4, bit 7
Alarm
0
X
X
No Alarm
1
0
0
Non-specific RDI alarm
1
1
1
Non-specific RDI alarm
1
0
1
TU-AIS, TU-LOP
1
1
0
TIM, UNEQ
NOTE:
The bit numbers above reference a byte whose least
significant bit is bit 8.