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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 4/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A —
21 E1 SDH Mapper
4
Datasheet
4.2.2
J2 Processing.........................................................................................27
4.2.2.1 J2 Memory Access....................................................................28
K4 Processing........................................................................................28
N2 Processing........................................................................................28
High Order Path Adaptation................................................................................29
Add/Drop Configuration
........................................................................................30
5.1
ADM Receive ......................................................................................................30
5.2
ADM Transmit .....................................................................................................30
5.2.1
Data Pass-Through................................................................................31
5.2.1.1 PTSOH......................................................................................31
5.2.1.2 PTTUGx ....................................................................................32
5.2.2
MTBDATA Drive Enable.........................................................................32
Application Information
.........................................................................................34
6.1
Port Mapping Configuration ................................................................................34
6.2
Telecom Bus Interface ........................................................................................35
6.2.1
Multiplexer Telecom Bus, Terminal Mode..............................................35
6.2.2
Multiplexer Telecom Bus, ADM Mode....................................................36
6.2.3
MTBDATA Output Enable......................................................................36
6.2.4
Demultiplexer Telecom Bus ...................................................................37
6.2.5
Telecom Bus Timing ..............................................................................37
6.3
Serial/Remote Alarm Processing Port.................................................................40
Test Specifications
..................................................................................................42
Microprocessor Interface & Register Definitions
.......................................50
8.1
Microprocessor Interface.....................................................................................50
8.1.1
Intel Interface .........................................................................................50
8.1.2
Motorola Interface ..................................................................................50
8.2
Interrupt Handling................................................................................................51
8.2.1
Interrupt Sources....................................................................................51
8.2.1.1 Interrupt Identification................................................................51
8.2.2
Interrupt Enables....................................................................................51
8.2.3
Interrupt Clearing ...................................................................................52
8.2.4
UpdateEn Configuration Bit....................................................................52
8.3
Register Address Map.........................................................................................52
8.3.1
Counter Access......................................................................................53
8.3.2
Register Notations and Definitions.........................................................53
8.4
Configuration Registers.......................................................................................55
8.4.1
GLOB_CONF
—
Global Configuration (000H).........................................55
8.4.2
TADD_CONF
—
Transmit Add Configuration (003
–
001H)......................56
8.4.3
TU_TS_CONF
—
TU Time Slot Configuration (161
–
175H).....................57
8.4.4
SIGLA_SET
—
Signal Label Setting (xEH)..............................................57
8.4.5
J2_MRST
—
J2 Memory Reset (008H)....................................................57
8.4.6
J2_ESDATA
—
J2 Expected String Data (xCH) ......................................58
8.4.7
J2_TSDATA
—
J2 Transmit String Data (xFH)........................................58
8.4.8
ERRI_CONF
—
Error Insert Configuration (xDH)....................................58
8.4.9
INT_CONF
—
Interrupt Configuration Register (00BH)...........................59
8.4.10 CHIP_ID
—
Chip Identification Number (00AH).......................................59
8.5
Interrupt Registers...............................................................................................60
4.2.3
4.2.4
4.3
5.0
6.0
7.0
8.0
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