LXT6251A
—
21 E1 SDH Mapper
58
Datasheet
8.4.6
J2_ESDATA
—
J2 Expected String Data (
x
CH)
x
=1
–
15H
This register is used to access the J2 memory for this receive channel. Successive reads or writes to
this register will increment a global counter that increments the address 0 through 15. A write to
global register 004H resets this counter to 0. This is not needed if all 16 bytes are always read or
written to J2 memory.
8.4.7
J2_TSDATA
—
J2 Transmit String Data (
x
FH)
x
=1
–
15H
This register is used to access the J2 memory for this transmit channel. Successive reads or writes
to this register will increment a global counter that increments the address 0 through 15. A write to
global register 004H resets this counter to 0. This is not needed if all 16 bytes are always read or
written to J2 memory.
8.4.8
ERRI_CONF
—
Error Insert Configuration (
x
DH)
x
=1
–
15H
Configures normal operation diagnostic functionality. These registers should be set to their default
configuration unless the unit is in diagnostic mode and is not transmitting valid traffic.
Bit
Name
Description
Type
Default
7:0
J2MemReset
No specific value. A write resets the memory pointer.
WO
00H
Bit
Name
Description
Type
Default
7:0
ExpcJ2StrgData
Bits <7:0> correspond to data <7:0>, respectively.
R/W
00H
Bit
Name
Description
Type
Default
7:0
XmtJ2StrgData
Bits <7:0> correspond to data <7:0>, respectively.
R/W
00H
Bit
Name
Description
Type
Default
7
Reserved
6
XmtJ2Access
1 = Allows the microprocessor to access the transmit J2 RAM via register
x
FH. Sixteen consecutive writes to
x
FH will fill the RAM. The address is
internally incremented after each write. A write to register 004H resets this
global address counter. Also forces the J2 output byte to 00H when globally
configured for standard unequipped, or 01H for supervisory unequipped.
0 = Disable
R/W
1
5
XmtHpaAisFrc
Force TU-AIS generation towards SDH network.
1 = Force
0 = Disable
R/W
0