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| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 37/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
37
6.2.4
Demultiplexer Telecom Bus
In both terminal and ADM configurations, the demultiplexer side Telecom Bus operates in a co-
directional mode, meaning that both the timing signals and the data are inputs to the LXT6251A.
The enable signals are coincident with the associated data on the bus.
DTBYCK
Input Telecom Bus byte clock at 6.48 MHz for STM0 or 19.44 MHz for
STM1
DTBDATA
Input byte wide Data. In STM-0, the data must consist of the 21 TU-12
signals in a 7 by TUG-2 format with the 2 fixed stuff columns at positions
30 and 59. The HPOH and SOH data on the bus is ignored, except as
required for ADM pass-through. In STM-1, the data must consist of a valid
TUG-3 payload active when DTBTUGEN is high. Other TUG-3, HPOH,
and SOH data is ignored, except as required for ADM pass-through.
DTBPAR
Input Parity bit calculated on each DTBDATA byte. This is an odd parity
calculation.
DTBJ0J1EN
Input Frame Position indicator, active high during both the J0 and J1
bytes. The J0 byte is identified when the DTBPAYEN is low, J1 when
DTBPAYEN is high. Optionally the MultiFrmSel configuration bit in
“
GLOB_CONF
—
Global Configuration (000H)
”
on page 55
can be set to
‘
1
’
, which adds a multiframe indication (byte H4=00 for TU-12 V1 byte
location) by detecting a two-byte wide J1 pulse every fourth frame. Note
the H4 indication can be active even when DTBPAYEN is Low.
DTBPAYEN
Input Payload Enable. A high on this input indicates that the DTBDATA
bus is being driven with the VC-3 or VC-4 payload. A low indicates the
location of the SOH bytes and the AU Pointer bytes.
DTBH4EN
Input indicates the multiframe start position. This signal must be active
high during the J1 byte following the multiframe when the H4 byte equals
‘
00
’
. This signal need not be present if the multiframe indication exists in
DTBJ0J1EN.
DTBTUGEN
Input used in STM-1 only. A high indicates that the DTBDATA bus is being
driven with the TUG-3 that is to be processed by the device. This signal
must also be High during the VC-4 HPOH byte, regardless of the TUG-3
it is enabling. In STM-0, this signal should be tied High.
Note:
Note on Telecom Bus Timing Reference: All Telecom Bus timing signals (DTBH4EN,
DTBPAYEN, DTBJ0EN and DTBTUGEN), and the output data (DTBPAR and DTBDATA) are
sampled on the falling edge of the DTBYCK clock. See Telecom bus timings in Figure 7 and
Figure 8.
6.2.5
Telecom Bus Timing
The following diagrams show the relation of timing reference and data signals on the Telecom bus.
In summary, if the timing reference signals (DTBJ0J1, DTBPAYEN) and the data are sourced from
the same device (co-directional timing), the data byte (i.e., J1) will be coincident with the J1
indicator. If the timing reference signals are sourced from a device that expects to receive data
(contra-directional timing), then the data will be received one half clock cycle later.
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