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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 20/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
20
Datasheet
To read the BIP counter registers, the microprocessor must first perform a write (any value) to
either (
x
6H,
x
7H), then wait at least three cycles of DTBYCK (0.5uS in STM-0) before reading the
two registers. The write action latches the counter value into the two registers, and clears the
counter to zero.
Consequent Actions:
REI indication will be sent to the transmitter via the SAP interface. The REI indication will be
set on the transmitted V5 byte unless the
XmtLptReiEn bit in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on page 58
is set to 0.
3.4.1.2
REI Detection (V5, bit 3)
The LPT block continually monitors the value of the REI bit and sets the REI interrupt bit in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
whenever it is found to be
‘
1
’
(an event).
These events are also counted with results available in
“
REI_CNT
—
Remote Error Indication
(REI) Counter (x9
–
x8H)
”
on page 64
. The counter will count to a maximum of 2047, which is
more than the maximum number of REI alarms within one second. If the counter overflows, an
Overflow interrupt is generated in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
and the
count recycles to zero.
To read the REI counter registers, the microprocessor must first perform a write (any value) to
either register (
x
8H,
x
9H), then wait at least three cycles of DTBYCK (0.5uS in STM-0) before
reading the two registers. The write action latches the counter values into the two registers, and
clears the counter to zero.
Consequent Actions: none
3.4.1.3
RFI Detection (V5, bit 4)
The LPT block continually monitors the value of the RFI bit and updates the RFI status bit in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
with its detected value (there is no filtering
or hysteresis on this bit). Whenever the RFI status bit changes the RFI interrupt bit in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
is set.
Consequent Actions: none
3.4.1.4
Signal Label Mismatch (V5, bits 5-7)
A signal label mismatch (SLM) status bit will be set in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
if the signal label does not match a valid pattern that can be processed by this chip for
five multiframes. Valid label values are 000 (Unequipped), 001 (Equipped, non-specific), and 010
(Equipped, asynchronous). It is cleared when the signal label equals a valid pattern for five
multiframes.
Whenever the SLM status bit changes the SLM interrupt bit in
“
TRIB_INT
—
Tributary Interrupt
(x1
–
x0H)
”
on page 61
is set.
Consequent Actions:
Outgoing E1 data on DTDx will be forced to AIS with derived 2.048MHz clock on DTCx
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