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| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 52/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
52
Datasheet
For example, when a tributary incurs a Signal Label Mismatch (SLM), if the interrupt is enabled,
the SlmAlm bit in the interrupt register will be set causing the device interrupt pin to become
active. The microprocessor would then read the tributary interrupt registers 00DH
–
00FH to
identify the tributary in alarm. Next the tributary IRQ registers
x
0H &
x
1H would be read to
identify the alarm. Finally, the status register
x
2H or
x
3H is read to determine the current alarm
state.
A read of the status register is usually the event that causes the interrupt bits to be cleared (active
bits in registers
x
0H &
x
1H). However, for Non-persistent events and counter overflow alarms a
read of the interrupt register (
x
0H or
x
1H) is all that is required. In fact, the primary difference
between each of interrupt types is the way their respective interrupt bits are
cleared
.
8.2.3
Interrupt Clearing
Status Alarm interrupt sources have their interrupt bits cleared when their status register is
read. For example, the interrupt due to a change in the incoming V5 RDI (bit 3 of interrupt
register
x
0H) is cleared when status register
x
2H is read. All of these alarm types have
associated status bits.
Event alarm interrupt sources have their interrupt bits cleared when their interrupt register is
read. For example, the interrupt due to a change in the incoming V5 REI (bit 5 of interrupt
register
x
0H) from a
‘
0
’
to a
‘
1
’
is cleared when register
x
0H is read. None of these alarm types
have associated status bits.
Interrupt sources due to counter overflows have their interrupt bits cleared when their interrupt
register is read. See below for description of counter access.
8.2.4
UpdateEn Configuration Bit
The LXT6251A provides an UpDateEn signal within
“
INT_CONF
—
Interrupt Configuration
Register (00BH)
”
on page 59
to help avoid the problem with an asynchronous microprocessor
interface with respect to the system data clock. With an asynchronous interface, it is possible,
though very rare, that a status register change could fail to set its associated interrupt register
because of the finite time taken to clear the interrupt registers after a status read. The time is three
byte clock cycles which is enough to provide a small window after each status read when alarms
detected will not cause an interrupt. This situation as described may be acceptable and will exist
when the UpDateEn bit is set to
‘
0
’
.
If the UpdateEn signal is set to
‘
1
’
, this problem is avoided by freezing both the status and interrupt
registers whenever any interrupt bit within a register is set.
We encourage programmers to set the UpdateEn bit to
‘
1
’
during the interrupt service routine to
avoid missing alarm information. The UpdateEn bit can be set to
‘
0
’
after the routine has
completed.
8.3
Register Address Map
The registers within the LXT6251A provide access for configuration, alarm monitoring and control
of the chip.
Table 17
shows the LXT6251A register address map. The registers are listed by
ascending address in the table.
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