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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 21/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
21
3.4.1.5
Unequipped Detection (V5, bits 5-7)
The Unequipped (UNEQP) status bit will be set in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on
page 63
if a
‘
000
’
is detected in the signal label for five consecutive multiframes. It is cleared when
the signal label equals a pattern other than
‘
000
’
for five consecutive multiframes.
Whenever the UNEQP status bit changes the UNEQP interrupt bit in
“
TRIB_INT
—
Tributary
Interrupt (x1
–
x0H)
”
on page 61
is set.
Consequent Actions:
If the global Unequipped configuration is not set to Supervisory, an RDI Indication will be
sent to the transmitter via the SAP interface. The RDI indication will be set on the transmitted
V5 byte unless the XmtLptRdiEn bit in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on
page 58
is set to 0. No indication is sent in Supervisory mode.
Outgoing E1 data on DTDx will be forced to AIS with derived 2.048MHz clock on DTCx
3.4.1.6
VC-AIS Detection (V5, bits 5-7)
If the signal label is detected as
‘
111
’
in any one multiframe, a VC-AIS alarm will be indicated on
the SAP bus. There is no internal alarm or interrupt associated with this alarm, and no hysteresis
filtering. If the SAP bus is used to control protection switching at the TU-12 level, it is
recommended that hysteresis filtering be added to this alarm in the external circuit.
VC-AIS is treated like a signal label mismatch. Thus, consequent actions follow SLM actions.
Consequent Actions:
A VC-AIS/SF Indication will be output on the SAP interface.
3.4.1.7
RDI Detection (V5, bit 8)
The LPT block continually monitors the value of the RDI bit and updates the RDI status bit in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
with its detected value (after five
consecutive frames). Whenever the RDI status bit changes the RDI interrupt bit in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
is set.
Consequent Actions: none
3.4.2
J2 Processing
J2 Trace Identifier processing is supported on a per tributary basis for both transmit and receive
paths. Within the receive section of each tributary, the RxJ2Access bit in
“
TRIB_INTE
—
Tributary
Interrupt Enable (x5
–
x4H)
”
on page 62
controls the support for J2 processing. When RxJ2Access
is a
‘
1
’
, both the J2 Path Label Mismatch and the CRC-7 error detection alarms are completely
masked. In this state the microprocessor is also able to access the J2 RAM cell of the tributary. This
is the default state after a power-up condition. When RxJ2Access is
‘
0
’
, the two alarms are
enabled, and the microprocessor cannot access the J2 RAM.
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