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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 59/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
59
8.4.9
INT_CONF
—
Interrupt Configuration Register (00BH)
8.4.10
CHIP_ID
—
Chip Identification Number (00AH)
This register is read-only and is used to identify the version of the Chip.
4
XmtLptRdiEn
Enable/Disable automatic hardware updates of V5 RDI bit. Used when the
microprocessor needs direct control of RDI.
1 = Enable
0 = Disable
R/W
1
3
XmtLptRdiFrc
Force active status of V5 RDI. Also causes K4 ERDI bits to be set to
‘
111
’
.
1 = Force
0 = Disable
R/W
0
2
XmtLptReiEn
Enable/Disable automatic hardware updates of V5 REI bit. Used when the
microprocessor needs direct control of REI.
1 = Enable
0 = Disable
R/W
1
1
XmtLptReiFrc
Force active status of V5 REI.
1 = Force
0 = Disable
R/W
0
0
InvBip
Enable/Disable the insertion of BIP-2 bit errors. Used to test receiver
functions downstream. When set, both BIP values are inverted from their
calculated value.
1 = Enable
0 = Disable
R/W
0
Bit
Name
Description
Type
Default
7:4
Reserved
Unused
3
UpdateEn
Controls the tributary Status register update mechanism. When set to
‘
1
’
, an
interrupt in the IRQ register associated with the status register will freeze
both registers until the status register has been read. A
‘
0
’
allows updates to
the status registers every multiframe.
0 = Always update status every multiframe
1 = Disable status update if interrupt alarm
R/W
0
2
LOMIntEn
When set to
‘
1
’
, allows a LOM alarm to activate the INT pin.
0 = Disable INT output pin dependency
1 = Enable INT output pin dependency
R/W
0
1
TBParIntEn
When set to
‘
1
’
, allows a parity error detected on the receive telecom bus to
activate the INT pin.
0 =Disable INT output pin dependency
1 = Enable INT output pin dependency
R/W
0
0
MasIntEn
Master Interrupt Enable; disables the INT output from chip.
0 = Disable
1 = Enable
R/W
0
Bit
Name
Description
Type
Default
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