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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 24/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
24
Datasheet
3.4.5.1
TU-AIS Alarm
V1/V2 = FFh for 8 consecutive multiframes
3.4.5.2
TU-LOP Alarm
V1/V2 invalid for 8 consecutive multiframes
3.4.5.3
Signal Label Mismatch
Signal Label invalid for 5 consecutive multiframes. A VC-AIS is also considered as an SLM.
3.4.5.4
Unequipped Alarm
Signal Label set to
‘
000
’
for 5 consecutive multiframes (either supervisory or non-supervisory
mode)
3.4.5.5
J2 Path Label Mismatch
16 byte J2 string has correct CRC-7 but does not match expected value.
The AIS consequent action from these alarms cannot be disabled with the exception of the J2
mismatch, which can be disabled via the use of the RxJ2Access bit. A Loss of multiframe should
also cause an E1 AIS condition, however there is no direct action taken by the device to generate
the AIS, the incoming Telecom bus data should already be in AIS.
3.5
Low Order Path Adaptation
After processing by the Path Overhead Terminator, the data is passed to the lower order path
adaptation (LPA) block. First, the three C1C2 bits are processed and a majority decision made as to
the value of the two stuffing indicator bits. A majority of 1
’
s for Cx indicates the associated Sx bit
is data, while majority
’
s indicates the Sx bit is stuff and should be ignored. This is then used
along with other timing inputs to extract the E1 payload data.
The data at this point is still parallel and therefore needs to be converted to serial and a relatively
smooth 2.048MHz clock generated. The degapper circuit performs these functions.
3.5.1
Desynchronizer
The LXT6251A implements a bit leaking function to reduce the multiplexing jitter that is created
during both the E1 to VC-12 stuffing process and SDH pointer movements at both the AU and TU
level. The input to the degapper is the byte parallel clock, byte data, TU timing information, and
indications of pointer movement from the TU level. The degapper block first interprets the stuffing
indicators and extracts the proper data, then attempts to smooth the clock, anticipating gaps created
by the frame, TU pointer movements, and stuffing. The output of the degapper directly feeds to
output pins (DTCx/DTDx) and consists of a relatively smooth E1 clock (and NRZ data) in which
the large gaps from pointer movements have been distributed over a period of time. In order for the
E1 output to conform to G.783 residual jitter requirements, an external jitter attenuation circuit is
required, such as that available in Intel
’
s octal digital interface, the LXT6282 or Intel
’
s LXT318
Line Interface with Jitter Attenuator.
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