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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 62/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
62
Datasheet
8.5.4
TRIB_INTE
—
Tributary Interrupt Enable (
x
5
–
x
4H)
x
=1
–
15H;
x
5H=Bits<15:8>,
x
4H=Bits<7:0> (Byte access only)
Each tributary has a set of these registers that can be used to enable an interrupt source for a
particular tributary. The Reset default is not enabled (
‘
0
’
).
4
ReiOvrFlw
This alarm indicates the REI counter has overflowed. The counter will rollover to
0 and continue counting.
R
X
3
Rdi
This alarm indicates the V5 RDI bit was set to
‘
1
’
for five consecutive
multiframes.
R
X
2
Rfi
This alarm indicates the V5 RFI bit was set to
‘
1
’
.
R
X
1
Slm
This alarm indicates that a Signal Label Mismatch has occurred. This alarm is
asserted if the Signal Label is detected to be a value other than
‘
000
’
(Uneq),
‘
001
’
(Equip, non specific), or
‘
010
’
(Equip, async) for five consecutive frames.
Removal of the alarm also requires five consecutive frames.
R
X
0
UnEqp
This alarm indicates that the Signal Label in V5 is detected as
‘
000
’
for five
consecutive frames. Removal of the alarm also requires five consecutive
frames.
R
X
Bit
Name
Description
Type
Default
Bit
Name
Description
Type
Default
15:14
Reserved
Unused
13
RxJ2Access
1= Allows the microprocessor to control access to the expected J2 RAM
via register
x
CH. Sixteen consecutive writes to
x
CH will fill the RAM. The
address is internally incremented after each write. A write to register
004h will reset this global counter. Also disables both the TIM and CRC7
alarm associated with J2 so no alarms or RDI feedback is generated
during configuration of the expected J2 string.
R/W
1
12
TuNDFIntEn
1 = Enable
0 = Disable
R/W
0
11
TimIntEn
1 = Enable
0 = Disable
R/W
0
10
Crc7ErrIntEn
1 = Enable
0 = Disable
R/W
0
9
TuLopIntEn
1 = Enable
0 = Disable
R/W
0
8
TuAisIntEn
1 = Enable
0 = Disable
R/W
0
7
Bip2IntEn
1 = Enable
0 = Disable
R/W
0
6
Bip2OvrFlwInt
En
1 = Enable
0 = Disable
R/W
0
5
ReiIntEn
1 = Enable
0 = Disable
R/W
0
4
ReiOvrFlwIntE
n
1 = Enable
0 = Disable
R/W
0
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