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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 19/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
19
3.3.1.2
TU Loss of Pointer (LOP)
If an invalid pointer state is detected in the TU pointer, the TU-LOP status bit in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
is set. An invalid pointer state is entered from either the
normal or AIS pointer state after 8 consecutive invalid pointer values or 8 consecutive NDF
pointers are detected. It is exited when either the LOP or Normal states are entered at which time
the TU-LOP status bit in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
is cleared.
Whenever the TU-LOP status changes the TU-LOP interrupt bit in
“
TRIB_INT
—
Tributary
Interrupt (x1
–
x0H)
”
on page 61
is set.
Consequent Actions:
An RDI alarm will be sent to the transmitter via the SAP interface. The RDI alarm will be set
in the transmitted V5 byte unless the XmtLptRdiEn bit in
“
ERRI_CONF
—
Error Insert
Configuration (xDH)
”
on page 58
is set to 0
Outgoing E1 data on DTDx will be forced to AIS with derived 2.048 MHz clock on DTCx.
3.4
Low Order Path Termination
After the TU Timing control has been updated by the pointer interpreter, the received data is
processed by the lower order path termination (LPT) block which terminates the POH bytes of each
VC-12, and records all information extractable from the POH for processing by the
microprocessor. For the V5 byte this includes counting BIP-2 and REI errors and monitoring the
RDI, RFI and signal label bits. For the J2 Path Trace byte this includes monitoring the Path trace
identification and CRC-7 alarms, and for the K4 byte this includes monitoring enhanced RDI
information. All alarm indications and counts are available via the microprocessor interface, with
the RDI, REI, VC-AIS, and BIP errors additionally fed to the Serial alarm port (SAP) for real-time
tributary alarm indication and remote alarm processing.
3.4.1
V5 Processing
3.4.1.1
BIP-2 Errors (V5, bits 1,2)
The LPT block continually calculates the BIP-2 value by generating a two-bit parity, starting with
V5. After receiving the 140 bytes in a multiframe, the calculated value is compared with the first
two bits of the next V5 and if a mismatch between the calculated and received BIP-2 is detected a
BIP-2 error interrupt is generated in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
. BIP-
2 mismatches are also counted with results available in
“
BIP2_ERRCNT
—
BIP2 Error Counter
(x7
–
x6H)
”
on page 63
. The BIP2 counters can be configured from
“
GLOB_CONF
—
Global
Configuration (000H)
”
on page 55
to count either two possible counts per multiframe (bit count) or
one possible count per multiframe (block count). The counter will count to a maximum of 4095,
which exceeds the maximum number of bit alarms in one second and the maximum number of
block errors in two seconds. If the counter overflows, an Overflow interrupt is generated in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
and the count recycles to zero.
Figure 5. V5 Byte
REI
RFI
RDI
4
3
2
1
8
7
6
5
Signal Label
BIP 2
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