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参数资料
| 型号： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 27/76页 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
27
Two bits in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on page 58
can modify the setting
of the REI bit. First, the XmtLptReiEn bit can be set to
‘
0
’
to disable the automatic response to the
RAP data. By default this bit is set to
‘
1
’
. Second, the XmtLptRdiFrc can be set to
‘
1
’
to force the
REI bit to be set to
‘
1
’
as long as this register bit is set. By default this bit is set to
‘
0
’
.
4.2.1.3
RFI Bit
The Remote Failure Indication bit as of yet has no standard definition that would allow automatic
generation with the LXT6251A. Therefore, the RFI bit can only be set by the microprocessor via
the RFISet bit in
“
SIGLA_SET
—
Signal Label Setting (xEH)
”
on page 57
.
4.2.1.4
Signal Label
The transmitted signal label is set to the value contained in the three SigLabelSet bits in
“
SIGLA_SET
—
Signal Label Setting (xEH)
”
on page 57
. By default, the value is set to
‘
010
’
which indicates the VC-12 is mapped asynchronously. This value can be set to
‘
001
’
for equipped
non-specific, or to
‘
000
’
to indicate the channel is unequipped.
Setting the SigLabelSet bits to
‘
000
’
indicates that a TU tributary is unused. By doing so, the chip
will generate an unequipped VC-12 signal. If the UNEQMode bit in
“
GLOB_CONF
—
Global
Configuration (000H)
”
on page 55
is set to
‘
0
’
, the result will be a VC-12 with all bytes set to
‘
0
’
except the V5 BIP-2. If UNEQMode is set to
‘
1
’
, indicating Supervisory Unequipped mode, the
resulting unequipped signal will additionally contain a valid J2, valid REI and RDI bits within the
V5 byte, and N2 set to 00h.
It is important to set the Signal Label to a valid value. An invalid value will be detected in a
receiver as a Signal Label mismatch alarm with a consequent action of generating an AIS signal at
the output E1 port.
4.2.1.5
RDI Bit
The RDI bit is updated every multiframe by monitoring the receive side status data on the Remote
Alarm Port (RAP). The RAP port is further described in
“
Serial/Remote Alarm Processing Port
”
on
page 40
. If the corresponding receive side TU-12 tributary detects defects consisting of TU-AIS,
TU-LOP, J2 TIM, or UNEQ, the RAP port will indicate to the transmit LPT block that the RDI bit
should be set to
‘
1
’
. There are two bits in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on
page 58
that can modify the setting of the RDI bit. First, the XmtLptRdiEn bit can be set to
‘
0
’
to
disable the automatic response to the RAP data. By default this bit is set to
‘
1
’
. Second, the
XmtLptRdiFrc can be set to
‘
1
’
to force the RDI bit to be set to
‘
1
’
as long as this register bit is set.
By default this bit is set to
‘
0
’
.
4.2.2
J2 Processing
J2 Trace Identifier processing support can be enabled on a tributary per tributary basis for the
transmit path. Within the transmit section of each tributary, the XmtJ2Access bit in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on page 58
controls the support for J2
processing. When XmtJ2Access is a
‘
1
’
, the power up default state, J2 transmission is disabled,
and the value
‘
00h
’
(Unequipped mode) or
‘
01
’
h (Supervisory Unequipped mode) is sent on every
J2 byte. Additionally, in this state the microprocessor is able to read and write to the J2 RAM cell
of the tributary. When XmtJ2Access is
‘
0
’
, the value contained in the J2 RAM is transmitted, and
the microprocessor is not able to access the J2 RAM.
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