STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
157
When the 56 kbit/s NxDS0 mode is selected, only the first 7 bits of the selected
time slots are sampled from the backplane and the 8th bit is gapped out. When
the 64 kbit/s NxDS0 mode is selected, all 8 bits of the selected time slots are
sampled from the backplane.
The 64 kbit/s NxDS0 with F-bit mode is intended to support ITU recommendation
G.802. This mode is only valid when the E1/T1B register bit is a logic 1 (E1
mode is selected). The operation is the same as the 64 kbit/s NxDS0 mode,
except that the framing bit is sampled. The F-bit is always sampled during the
first bit of time slot 26. The remaining seven bits of time slot 26 are not sampled.
To properly insert a G.802 formatted T1, the IDLE_DS0 bits must be set to logic 0
for time slots 1 through 15 and 17 through 26, and the IDLE_DS0 bits must be
set to logic 1 for time slots 27 through 31.
CMODE:
The clock mode (CMODE) bit determines whether the BTCLK pin is an input
or output. When CMODE is a logic 0, clock master mode is selected and the
BTCLK output is derived from the integral clock synthesizer. Depending on
the mode of operation, BTCLK may have a burst frequency of up to
2.048 MHz and may be gapped to support sub-rate applications. In T1 mode,
CMODE can only be logic 0 if the backplane rate is 1.544 Mbit/s
(RATE[1:0]=00) and CMS=0. In E1 mode, CMODE can only be logic 0 if the
backplane rate is 2.048 Mbit/s (RATE[1:0]=01) and CMS=0.
When CMODE is a logic 1, clock slave mode is selected and BTCLK is an
input.
DE:
The data edge (DE) bit determines the edge of BTCLK on which BTPCM and
BTSIG are sampled. If DE is a logic 0, BTPCM and BTSIG are sampled on
the falling edge of BTCLK. If DE is a logic 1, BTPCM and BTSIG are
sampled on the rising edge of BTCLK.
FE:
The framing edge (FE) bit determines the edge of BTCLK on which the frame
pulse (BTFP) pulse is sampled or updated. If FE is a logic 0, BTFP is
sampled or updated on the falling edge of BTCLK. If FE is a logic 1, BTFP is
sampled or updated on the rising edge of BTCLK. In the case where FE is
not equal to DE, BTFP is sampled one clock edge or updated three clock
edges before BTPCM and BTSIG are sampled.
CMS:
The clock mode select (CMS) bit determines the BTCLK frequency multiple.
If CMS is a logic 0, BTCLK is at the backplane rate. If CMS is a logic 1,