STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
197
Register 058H: PMON Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
INTE
XFER
OVR
X
X
X
X
X
0
0
0
R/W
R
R
This register contains status information indicating when counter data has been
transferred into the holding registers and indicating whether the holding registers
have been overrun.
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the
transfer clock has caused the counter values to be stored in the holding
registers. A logic 1 bit in the INTE position enables the generation of an
interrupt via the INTB output; a logic 0 bit in the INTE position disables the
generation of an interrupt.
XFER:
The XFER bit indicates that a transfer of counter data has occurred. A logic 1
in this bit position indicates that a latch request, initiated by writing to one of
the counter register locations or the Global PMON Update register, was
received and a transfer of the counter values has occurred. A logic 0 indicates
that no transfer has occurred. The XFER bit is cleared (acknowledged) by
reading this register.
OVR:
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit
position indicates that a previous transfer (indicated by XFER being logic 1)
has not been acknowledged before the next transfer clock has been issued
and that the contents of the holding registers have been overwritten. A logic 0
indicates that no overrun has occurred. The OVR bit is cleared by reading this
register.