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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
401
14.6 Using the Line Receiver
The line receiver must be properly initialized for correct operation. Several
register bits must be programmed, and a RAM table must be initialized.
Note that two registers must be programmed to non-default values. The
Reserved bit of the RLPS Equalizer Configuration register must be set to logic 1.
The EQ_VREF[5:0] bits of the RLPS Equalizer Voltage Reference register must
be programmed to 2CH (‘b101100) for T1 mode or 34H (‘b110100) for E1 mode.
Since the line receiver supports both E1 and T1 standards over either short haul
or long haul cables, the line receiver has two normal modes of operation, as
selected by the T1/E1B bit of the Global Configuration register. Table 107 and
Table 108 contain the values to be programmed into the equalizer RAM for T1
and E1 mode, respectively.
The RLPS equalizer RAM content is programmed by the RLPS Equalization
Indirect Data registers (0D8H to 0DBH) for each address location. The address
location is given by the quadrant’s RLPS Equalization Indirect Address register
(0FCH). A read or write request is done by setting the RWB bit in the quadrant’s
RLPS Equalization Read/WriteB Select register (0FDH). Table 106 below
summarizes the values the RLPS registers are to contain.
Table 106 - RLPS Register Programming
Data Value
Binary
Hex
Register
Address
Register Name
XX000XX1
01H
0F8H
RLPS Configuration and Status
X000X000
00H
0F9H
RLPS ALOS Detection/ Clearance
Threshold
00000001
01H
0FAH
RLPS ALOS Detection Period
00000001
01H
0FBH
RLPS ALOS Clearance Time
00000000
00H
0FCH
RLPS Equalization Indirect Address
1XXXXXXX
80H
0FDH
RLPS Equalization RAM Read/WriteB
Select
00000000
00H
0FEH
RLPS Equalizer Loop Status and
Control