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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
226
be enabled to work on only the first 7 bits of a channel (for Nx56 kbps
fractional T1) using the Nx56k_DET and Nx56k_GEN bits in the Pattern
Generator/Detector Positioning/Control register. The PRGD can also be
enabled to work on the entire DS1, including framing bits, using the
UNF_GEN and UNF_DET bits in the Pattern Generator/Detector
Positioning/Control register.
LOOP:
The LOOP bit enables the DS0 loopback. When the LOOP bit is set to a
logic 1, transmit data is overwritten with the corresponding channel data from
the receive line. When the Receive Elastic Store (RX-ELST) is bypassed, it is
used to align the receive line data to the transmit frame. When RX-ELST is
enabled, however, it is unavailable to facilitate per-DS0 loopbacks.
Data inversion, idle, loopback and test pattern insertion/checking are performed
independent of the transmit framing format. DS0 loopback takes precedence
over digital milliwatt pattern insertion. Next in priority is test pattern insertion,
which, in turn, takes precedence over idle code insertion. Data inversion has the
lowest priority. When test pattern checking is enabled, the transmit data is
compared before DS0 loopback, digital milliwatt pattern insertion, idle code
insertion or data inversion is performed. None of this prioritizing has any effect
on the gapping of BTCLK in NxDS0 mode. That is, if both DS0 loopback and
idle code insertion are enabled for a given channel while in NxDS0 mode, the
DS0 will be looped-back, will not be overwritten with idle code, and BTCLK will
be gapped out for the duration of the channel. Similarly, none of the prioritizing
has any effect on the generation of test patterns from the PRGD, only on the
insertion of that pattern. Thus, if both DMW and TEST are set for a given DS0,
and RXPATGEN = 0, the test pattern from the PRGD will be overwritten with the
digital milliwatt code. This same rule also applies to test patterns inserted via the
UNF_GEN bit in the Pattern Generator/Detector Positioning/Control register.
ZCS0, ZCS1:
The ZCS0 and ZCS1 bits select the zero code suppression used as follows:
Table 47
- Transmit Zero Code Suppression Formats
ZCS0
ZCS1
Description
0
0
0
1
No Zero Code Suppression
“Jammed bit 8" - Every bit 8 is forced to a one. This
may be used for 56 kbit/s data service. This is the only
code that should be inserted in E1 mode.