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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
376
5. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can
be written. When in this state, either a timer can be used to determine when
sufficient bytes are available in the FIFO or the user can wait until the LFILLI
interrupt is set, indicating that the FIFO depth is at the lower threshold limit.
If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state
earlier, but has since emptied out some of its data bytes and now has space
available in its FIFO for more data.
6. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower
threshold limit. If there is more data to transmit, then it should be written to
the TDPR Transmit Data register before an underrun occurs. If there is no
more data to transmit, then an EOM should be set at the end of the last
packet byte. Flags will then be transmitted once the last packet has been
transmitted.
If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lower-
threshold state earlier, but has since been refilled to a level above the lower-
threshold level.
14.2.3 Automatic transmission mode using polling:
The TDPR automatically transmits a packet once it is completely written into the
TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level
exceeds the programmable Upper Transmit Threshold. The CRC bit can be set
to logic 1 so that the FCS is generated and inserted at the end of a packet. The
TDPR Lower Interrupt Threshold should be set to such a value that sufficient
warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits
are all set to logic 0 since packet transmission is set to work with a periodic
polling procedure. The following procedure should be followed to transmit HDLC
packets:
1. Wait until data is available to be transmitted, then go to step 2.
2. Read the TDPR Interrupt Status register.
3. If FULL=1, the TDPR FIFO is full and no further bytes can be written.
Continue polling the TDPR Interrupt Status register until either FULL=0 or
BLFILL=1. Then, go to either step 4 or 5 depending on implementation
preference.
4. If BLFILL=1, the TDPR FIFO depth is below its lower threshold limit. Write
the data into the TDPR Transmit Data register. Go to step 6.