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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
280
Register 09AH: E1 FRMR CRC Error Counter – MSB/Timeslot 16 Extra Bits
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
OVR
0
0
X
X
X
X
X
X
NEWDATA
X[3]
Y
X[1]
X[0]
CRCERR [9]
CRCERR [8]
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
This register contains the most significant two bits of the 10-bit CRC error
counter value, updated every second.
NEWDATA:
The NEWDATA flag bit indicates that the CRCERR counter register contents
have been updated with a new count value accumulated over the last 1
second interval. It is set to logic 1 when the CRC error counter data is
transferred into the counter registers, and is reset to logic 0 when this register
is read. This bit can be polled to determine the 1 second timing boundary
used by the FRMR.
OVR:
The OVR flag bit indicates that the CRCERR counter register contents have
not been read within the last 1 second interval, and therefore have been over-
written. It is set to logic 1 if CRC error counter data is transferred into the
counter registers before the previous data has been read out, and is reset to
logic 0 when this register is read.
X[3], Y, X[1], X[0]:
Reading these bits returns the value of the Extra bits (X[3] and X1:0]) and the
Remote Signaling Multiframe Alarm bit (Y) in Frame 0, Timeslot 16 of the last
received signaling multiframe. These bits are updated upon generation of the
IFPI interrupt on NFAS frames. They map to timeslot 16 as shown in Table