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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
198
Registers 059-05FH: Latching Performance Data
The Performance Data registers for a single framer are updated as a group by
writing to any of the PMON count registers (addresses 059H-05FH). A write to
one (and only one) of these locations loads performance data located in the
PMON into the internal holding registers. Alternatively, the Performance Data
registers are updated by writing to the Revision/Chip ID/Global PMON Update
register (address 00DH). The data contained in the holding registers can then be
subsequently read by microprocessor accesses into the PMON count register
address space. The latching of count data, and subsequent resetting of the
counters, is synchronized to the internal event timing so that no events are
missed.
The PMON is loaded with new performance data within 3.5 recovered clock
periods of the latch performance data register write. With nominal line rates, the
PMON registers should not be polled until 2.3 μsec have elapsed from the "latch
performance data" register write.
When the COMET is reset, the contents of the PMON count registers are
unknown until the first latching of performance data is performed.