STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
259
Register 085H: E1 TRAN Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
SIGMFI
NFASI
MFI
SMFI
FRMI
X
X
X
X
X
X
X
X
R
R
R
R
R
When the E1/T1B bit of the Global Configuration register is a logic 0, this register
is held reset.
FRMI:
The FRMI interrupt bit is set to logic 1 on frame boundaries, it is set on
timeslot 30, bit 7 of every frame in the transmit data stream. The contents of
this register are cleared to logic 0 after the register is read.
SMFI:
The SMFI interrupt bit is set to logic 1 on CRC-4 sub multiframe boundaries,
it is set on timeslot 30, bit 7 of frame 0 of the CRC submultiframe in the
transmit data stream. The contents of this register are cleared to logic 0 after
the register is read.
MFI:
The MFI interrupt bit is set to logic 1 on CRC-4 multiframe boundaries, it is
set on timeslot 30, bit 7 of frame 0 of the CRC multiframe in the transmit data
stream. The contents of this register are cleared to logic 0 after the register is
read.
NFASI:
The NFASI interrupt bit is set to logic 1 on NFAS frame boundaries, it is set
on timeslot 30, bit 7 of the NFAS frame in the transmit data stream. The
contents of this register are cleared to logic 0 after the register is read.