STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
292
sequences (depending on the FLGSHARE bit setting) after the performance
report frame. If the ABT bit is still set, the TDPR will then transmit the Abort
sequence again.
EOM:
The EOM bit indicates that the last byte of data written in the Transmit Data
register is the end of the present data packet. If the CRC bit is set then the
16-bit FCS word is appended to the last data byte transmitted and a
continuous stream of flags is generated. The EOM bit is cleared upon a write
to the TDPR Transmit Data register.
PREN:
The PREN bit enables performance reports from the T1-APRM to be
transmitted. When PREN is a logic 1, the message arbitrator circuit will insert
the T1-APRM performance report as soon as it is finished any packet whose
transmission is already in progress and the delimiting flags. When PREN is a
logic 0, the message arbitrator circuit will ignore requests from the T1-APRM.
This bit has no effect for TDPR #2 and TDPR #3.
FIFOCLR:
The FIFOCLR bit resets the TDPR FIFO. When set to logic 1, FIFOCLR will
cause the TDPR FIFO to be cleared. There is a maximum delay of one T1 or
E1 clock cycle between the setting of this register bit and the execution of the
FIFO clear operation.
FLGSHARE:
The FLGSHARE bit configures the TDPR to share the opening and closing
flags between successive frames. If FLGSHARE is logic 1, the opening and
closing flags between successive frames are shared. If FLGSHARE is
logic 0, separate closing and opening flags are inserted between successive
frames.