STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
375
14.2.2 TDPR Interrupt Routine:
The following procedure should be carried out when an interrupt is detected on
INT:
1. Read the TDPR Interrupt Status register.
2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has
been corrupted and needs to be retransmitted. When the UDRI bit transitions
to logic 1, one Abort sequence and continuous flags will be transmitted. The
TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear
the underrun, the TDPR Interrupt Status/UDR Clear register should be written
with any value.
3. If OVRI=1, then the FIFO has overflowed. The packet which the last byte
written into the FIFO belongs to has been corrupted and must be
retransmitted. Other packets in the FIFO are not affected. Either a timer can
be used to determine when sufficient bytes are available in the FIFO or the
user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is
at the lower threshold limit.
If the FIFO overflows on the packet currently being transmitted (packet is
greater than 128 bytes long), an Abort signal is scheduled to be transmitted,
the FIFO is emptied, and then flags are continuously sent until there is data to
be transmitted. The FIFO is held in reset until a write to the TDPR Transmit
Data register occurs. This write contains the first byte of the next packet to
be transmitted.
4. If OVRI=1, then the FIFO has overflowed. The packet which the last byte
written into the FIFO belongs to has been corrupted and must be
retransmitted. Other packets in the FIFO are not affected. When an overflow
occurs, the OVR output signal is set. Either a timer can be used to determine
when sufficient bytes are available in the FIFO or the user can wait until the
LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold
limit. The OVR output signal remains set until the next write to the TDPR
Transmit Data register. This write contains the first byte of the next packet to
be transmitted.
If the FIFO overflows on the packet currently being transmitted (packet is
greater than 128 bytes long), the OVR output signal is set, an Abort signal is
scheduled to be transmitted, the FIFO is emptied, and then flags are
continuously sent until there is data to be transmitted. The FIFO is held in
reset until a write to the TDPR Transmit Data register occurs. This write
contains the first byte of the next packet to be transmitted.