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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
315
Register 0E0H: PRGD Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR[1]
PDR[0]
QRSS
PS
TINV
RINV
AUTOSYNC
MANSYNC
0
0
0
0
0
0
1
0
PDR[1:0]:
The PDR[1:0] bits select the content of the four pattern detector registers to
be any one of the pattern receive registers, the error count holding registers,
or the bit count holding registers. The selection is shown in the following
table:
Table 67
- Pattern Detector Register Configurations
PDR[1:0]
PDR#1
PDR#2
PDR#3
PDR#4
00, 01
Pattern Receive
(LSB)
Pattern
Receive
Pattern
Receive
Pattern
Receive
(MSB)
Error Count
(MSB)
Bit Count
(MSB)
10
Error Count
(LSB)
Bit Count (LSB)
Error Count
Error Count
11
Bit Count
Bit Count
QRSS:
The quasi-random signal source (QRSS) bit enables the zero suppression
feature required when generating a QRSS sequence. More specifically, a
one is forced in the transmit stream when QRSS is a logic 1 and the following
14 bit positions in the transmit bit stream generator are all zeros. When
QRSS is a logic 0, the zero suppression feature is disabled. Note that the
QRSS bit is also interpreted by the PRGD receiver. Accordingly, the receiver