STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
239
Register 078H: T1 APRM Configuration/Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
R
U1
U2
CONT_CRC
INTE
AUTOUPDATE
X
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
AUTOUPDATE:
The AUTOUPDATE bit controls the automatic updating of the performance
report on a per second basis. If this bit is set to a logic 1, the Performance
Report Messages are generated and updated once a second. When
AUTOUPDATE is set to a logic 0, the performance report is updated
manually by toggling the MAN_LOAD register bit.
INTE:
The INTE bit enables the interrupt output pin. When INTE is set to a logic 1,
a logic 1 in the INTR bit in the T1 APRM Interrupt Status register asserts the
INTB output low. INTR is disabled from generating interrupts when INTE is
set to a logic 0.
CONT_CRC:
The CONT_CRC is the Continuous CRC bit. When set to logic 1, the SE and
G6 bits in the Performance Report are set to1 and G1, G2, G3, G4, G5 and
FE are set to 0. When reset to logic 0, the Gn (n = [1..5]), FE and SE bits are
set according to the received CRC errors.
U1, U2:
The U1, U2 bits are under study for synchronization. Their default value is 0.
These bits require two updating cycles before they are included in the
performance report.