STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
302
Registers 0C2H (#1), 0CAH (#2), 0D2H (#3): RDLC Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
FE
OVR
COLS
PKIN
PBS[2]
PBS[1]
PBS[0]
INTR
X
X
X
X
X
X
X
X
INTR:
The interrupt (INTR) bit is logic 1 if the RDLC has an active interrupt status.
An RDLC interrupt is generated
1) when the number of bytes specified by the INTC[6:0] bits of the RDLC
Interrupt Control register have been received on the data link and have
been written into the FIFO,
2) immediately upon detection of a FIFO buffer overrun, as indicated by the
OVR in this register,
3) immediately upon writing the last byte of a packet into the FIFO,
4) immediately upon writing the last byte of an aborted packet, or
5) immediately upon detection of the transition from receiving all ones to
flags, as indicated by a “001” code in PBS[2:0].
If INTR is logic 1, follow the procedure described in section 14.3: Using the
Internal HDLC Receivers
PBS[2:0]
The packet byte status (PBS[2:0]) bits indicate the status of the data last read
from the FIFO. The bits are encoded as follows:
Table 65
- Receive Packet Byte Status
PBS[2:0]
Significance
000
Data byte read from the FIFO is not special