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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
299
Registers 0C0H (#1), 0C8H (#2), 0D0H (#3): RDLC Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Reserved
MEN
MM
TR
EN
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
EN:
The enable (EN) bit controls the overall operation of the RDLC. When EN is
set to logic 1, RDLC is enabled; when set to logic 0, RDLC is disabled. When
the RDLC is disabled, the FIFO buffer and interrupts are all cleared. When
the RDLC is enabled, it will immediately begin looking for flags.
TR:
Setting the terminate reception (TR) bit to logic 1 forces the RDLC to
immediately terminate the reception of the current data frame, empty the
FIFO buffer, clear the interrupts, and begin searching for a new flag
sequence. The RDLC handles a terminate reception event in the same
manner as it would the toggling of the EN bit from logic 1 to logic 0 and back
to logic 1. Thus, the RDLC state machine will begin searching for flags. An
interrupt will be generated when the first flag is detected. The TR bit will reset
itself to logic 0 after a rising and falling edge have occurred on the CLK input,
once the write strobe (CBI[9]) goes high. If the Configuration Register is read
after this time, the TR bit value returned will be logic 0.
MEN:
Setting the Match Enable (MEN) bit to logic 1 enables the detection and
storage in the FIFO of only those packets whose first data byte matches
either of the bytes written to the Primary or Secondary Match Address
Registers, or the universal all ones address. When the MEN bit is logic 0, all
packets received are written into the FIFO.