STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
329
Register 0EFH: PRGD Pattern Detector #4
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
PD[31]
PD[30]
PD[29]
PD[28]
PD[27]
PD[26]
PD[25]
PD[24]
X
X
X
X
X
X
X
X
PD[31:0]:
Reading PD[31:0] returns the contents of the pattern detector data register
selected by the PDR[1:0] bits in the control register. All three detector data
registers are updated during an accumulation interval.
When PDR[1:0] is set to 00 or 01, reading PD[31:0] returns the contents of
the pattern receive register. The 32 bits received immediately before the last
accumulation interval are present on PD[31:0]. PD[0] contains the bit
received immediately prior to the last accumulation.
When PDR[1:0] is set to 10, reading PD[31:0] returns the contents of the
error counter holding register. The value in this register represents the
number of bit errors that were accumulated during the last accumulation
interval, up to a maximum (saturation) value of 2
32
-1. Note that bit errors are
not accumulated while the pattern detector is out of sync.
When PDR[1:0] is set to 11, reading PD[31:0] returns the contents of the bit
counter holding register. The value in this register represents the total
number of bits that were received during the last accumulation interval, up to
a maximum (saturation) value of 2
32
-1. Note that bits are not counted while
the pattern detector is out of synchronization.
Writing to any of these registers or the Global PMON Update Register causes
them to be updated, and the internal counters reset. The XFERI bit in PRGD
Enable/Status register will go high once the update is complete, and an
interrupt will be generated if enabled.