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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
271
Register 094H: E1 FRMR Framing Status Interrupt Indication
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
C2NCIWI
OOFI
OOSMFI
OOCMFI
COFAI
FERI
SMFERI
CMFERI
X
X
X
X
X
X
X
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
A logic 1 in any bit position of this register indicates which framing status
generated an interrupt by changing state.
C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI:
C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI indicate when the
corresponding status has changed state from logic 0 to logic 1 or vice-versa.
FERI, SMFERI, CMFERI:
FERI, SMFERI, CMFERI indicate when a framing error, signaling multiframe
error or CRC multiframe error event has been detected; these bits will be set
if one or more errors have occurred since the last register read.
The interrupt indications within this register work independently from the interrupt
enable bits, allowing the microprocessor to poll the register to determine the
state of the framer. The contents of this register are cleared to logic 0 after the
register is read; the interrupt is also cleared if it was generated by any of the
Framing Status outputs.