STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
365
Figure 33
- Receive Backplane at 8.192 Mbit/s (T1 Mode)
TS 31
BRSIG
D
B C
A
BRFP
8.192 MHz BRCLK
(CMS = 0)
BRPCM
TS 0
F
X
X
X
A 8.192 Mbit/s backplane in T1 mode by setting the RATE[1:0] bits of the
Receive Backplane Configuration register to 'b11 and the E1/T1B bit of the
Global Configuration register to a logic 0. In Figure 24, BRFP, BRPCM and
BRSIG are configured to be updated on the falling edge of BRCLK by setting the
FE and DE bits of the Receive Backplane Configuration register to logic 0.
TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is
sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new
RATE[1:0].
In Figure 24, the MAP register bit is logic 0. As shown, every fourth time slot is
unused, starting with the first. If MAP is a logic 1, time slots 0 through 23 would
be used. The framing bit is presented during bit 0 of time slot 0, so that only bits
1 to 7 of time slot 0 are ignored. The TSOFF[6:0], BOFF_EN and BOFF[2:0]
register bits are all logic zero; therefore, BRFP is expected to be aligned to the
first bit of the frame.
Figure 34
- Receive Backplane at 8.192 Mbit/s (E1 Mode)
TS 31
TS 0
D
B C
A
X
X
BRSIG
BRFP
8.192 MHz BRCLK
(CMS = 0)
BRPCM
A 8.192 Mbit/s backplane in E1 mode by setting the RATE[1:0] bits of the
Receive Backplane Configuration register to 'b11 and the E1/T1B bit of the
Global Configuration register to a logic 1. In Figure 34, BRFP, BRPCM and
BRSIG are configured to be updated on the falling edge of BRCLK by setting the
FE and DE bits of the Receive Backplane Configuration register to logic 0.
TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is
sampled.