![](http://datasheet.mmic.net.cn/330000/PM4351_datasheet_16444271/PM4351_320.png)
STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
296
Register 0ACH (#1), 0B4H (#2), 0BCH (#3): TDPR Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
FULL
BLFILL
PRINTI
FULLI
OVRI
UDRI
LFILLI
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
Writing to this register will clear the underrun condition if it has occurred.
Consecutive writes to the TDPR Configuration and TDPR Transmit Data register
and reads of the TDPR Interrupt Status register should not occur at rates greater
than that of TCLKO.
LFILLI:
The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions
to empty or falls below the value of LINT[6:0] programmed in the TDPR
Lower Interrupt Threshold register. LFILLI will assert INTB if it is a logic 1 and
LFILLE is programmed to logic 1. LFILLI is cleared when this register is read.
UDRI:
The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the
TDPR was in the process of transmitting a packet when it ran out of data to
transmit. UDRI will assert INTB if it is a logic 1 and UDRE is programmed to
logic 1. UDRI is cleared when this register is read.
OVRI:
The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the
TDPR FIFO was already full when another data byte was written to the TDPR
Transmit Data register. OVRI will assert INTB if it is a logic 1 and OVRE is
programmed to logic 1. OVRI is cleared when this register is read.