STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
360
Figure 23
- Transmit Backplane at 4.096 Mbit/s (E1 mode)
TS 0
D
C
BTFP
4.096 M(CMS = 0)
BTPCM
BTSIG
X
TS 31
TS 1
X
X
TS 2
X
A
D
B
C
X
A
D
B
C
X
X
X
X
X
X
A 4.096 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits
of the Transmit Backplane Configuration register to 'b10 and the E1/T1B bit of
the Global Configuration register to a logic 1. In Figure 23, BTFP, BTPCM and
BTSIG are configured to be sampled on the rising edge of BTCLK by setting the
FE and DE bits of the Transmit Backplane Configuration register to logic 1.
TSOFF[6:0] is set to 'b0000000 so that the first of the two interleaved bytes is
sampled.
Figure 24
- Transmit Backplane at 8.192 Mbit/s (T1 mode)
TS 0
X
BTFP
8.192 MHz BTCLK
(CMS = 0)
BTPCM
BTSIG
X
X
X
X
TS 1
X
X
X
D
B C
A
X
X
X
F
X
X
X
X
X
X
A 8.192 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits
of the Transmit Backplane Configuration register to 'b11 and the E1/T1B bit of
the Global Configuration register to a logic 0. In Figure 24, BTFP, BTPCM and
BTSIG are configured to be sampled on the rising edge of BTCLK by setting the
FE and DE bits of the Transmit Backplane Configuration register to logic 1.
TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is
sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new
RATE[1:0].
In Figure 24, the MAP bit of the Transmit Backplane Frame Pulse Configuration
register is a logic 0. Therefore, every fourth time slot is unused, starting with
timeslot 0. The framing bit is sampled during bit 0 of time slot 0, so that only bits
1 to 7 of time slot 0 are ignored. If MAP is logic 1, the 24 T1 channels would be
aligned to the first 24 timeslots with the F-bit located in the last bit of the 32
nd
timeslot.