![](http://datasheet.mmic.net.cn/330000/PM4351_datasheet_16444271/PM4351_397.png)
STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
373
Table 83
- ESF FDL Processing
Action
Addr
Data
Effect
Write RXCE Receive Data
Link 1 Control Register
028H
20H
Select extraction of ESF
Facility Data Link for HDLC
receiver #1. (COMET must be
set up for ESF frame format.)
Select insertion of ESF Facility
Data Link from HDLC
transmitter #1. (COMET must
be set up for ESF frame
format.)
Write TXCI Transmit Data
Link 1 Control Register
038H
20H
14.2 Using the Internal HDLC Transmitters
It is important to note that the access rate to the TDPR registers is limited by the
rate of the transmit clock. The TDPR registers should be accessed at a rate no
faster than that of the transmit system clock.
To properly initialize the transmit HDLC controllers in transmit basic frame
alignment mode (FPTYP is logic 0), transmit multiframe alignment (FPTYP is
logic 1) must be configured for at least one multiframe (i.e., for at least one
multiframe period in frame pulse master mode or for at least one input frame
pulse in frame pulse slave mode). After this initialization, the FPTYP can be set
to any desired value.
Upon reset, the TDPR should be disabled by setting the EN bit in the TDPR
Configuration Register to logic 0 (default value). After making all initial
configurations to the TDPR, the EN bit should be set to logic 1 to enable the
TDPR and then the FIFOCLR bit should be set and then cleared to initialize the
TDPR FIFO. The TDPR is now ready to transmit.
To initialize the TDPR, the TDPR Configuration Register must be properly set. If
FCS generation is desired, the CRC bit should be set to logic 1. If the block is to
be used in interrupt driven mode, then interrupts should be enabled by setting
the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register
to logic 1. The TDPR operating parameters in the TDPR Upper Transmit
Threshold and TDPR Lower Interrupt Threshold registers should be set to the
desired values. The TDPR Upper Transmit Threshold sets the value at which the
TDPR automatically begins the transmission of HDLC packets, even if no
complete packets are in the FIFO. Transmission will continue until the current
packet is transmitted and the number of bytes in the TDPR FIFO falls to, or
below, this threshold level. The TDPR will always transmit all complete HDLC