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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
332
Register 0F1H: XLPG Control/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
OVRFLW
Reserved
Reserved
X
X
X
X
X
X
0
1
R
R/W
R/W
When the TUNI bit of the Transmit Line Interface Configuration register is a
logic 1, this register is held reset.
OVRFLW:
The overflow detection value bit (OVRFLW) indicates the presence or
absence of an overflow condition in the waveform computation pipeline. An
overflow occurs when the sum of the five unit interval (UI) samples exceeds
the maximum D/A value. The XLPG detects overflows and saturates the
output value to minimize their impact on the output signal. Overflows can
easily be eliminated by changing the waveform programming. This status bit
is set to logic 1 when an overflow condition is detected and it is reset to
logic 0 only when this register is read. It is suggested to read this register
twice after the programming of a new waveform and transmission of data to
ensure the maximum output amplitude is never exceeded.
Reserved:
The Reserved bits must remain in their default state for correct operation.