
6-28
SCSI SCRIPTS Instruction Set
When a Return instruction is executed, the value stored
in the Temporary (TEMP) register is returned to the DSP
register. The SYM53C895 does not check to see whether
the Call instruction has already been executed. It does
not generate an interrupt if a Return instruction is
executed without previously executing a Call instruction.
If the comparisons are false, the SYM53C895 fetches the
next instruction from the address pointed to by the DSP
register and the instruction pointer is not modied.
Interrupt Instruction
The SYM53C895 can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
dened by the Phase Compare, Data Compare, and
True/False bit elds.
If the comparisons are true, the SYM53C895 generates
an interrupt by asserting the IRQ/ signal.
The 32-bit address eld stored in the DMA SCRIPTS
Pointer Save (DSPS) register can contain a unique
interrupt service vector. When servicing the interrupt, this
unique status code allows the Interrupt Service Routine
to quickly identify the point at which the interrupt
occurred.
The SYM53C895 halts and the DMA SCRIPTS Pointer
(DSP) register must be written to before starting any
further operation.
Interrupt on the Fly Instruction
The SYM53C895 can do a true/false comparison of the
ALU carry bit or compare the phase and/or data as
dened by the Phase Compare, Data Compare, and
True/False bit elds.
If the comparisons are true, and the Interrupt-on-the-Fly
bit (Interrupt Status (ISTAT0) bit 2) is set, the
SYM53C895 asserts the Interrupt-on-the-Fly bit.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit eld corresponds to the three SCSI bus phase
signals that are compared with the phase lines latched
when SREQ/ is asserted. Comparisons can be
performed to determine the SCSI phase actually being
driven on the SCSI bus.
Table 6.5 describes the possible