
3-2
PCI Functional Description
operating registers. For all PCI cycles except conguration cycles, the
SYM53C895 registers are located on the 256-byte block boundary
dened by the base address assigned through the congured register.
The SYM53C895 operating registers are available in both the upper and
lower 128-byte portions of the 256-byte space selected.
At initialization time, each PCI device is assigned a base address (in the
case of the SYM53C895, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
SYM53C895 compares its assigned base addresses with the value on
the Address/Data bus during the PCI address phase. If there is a match
of the upper 24 bits, the access is for the SYM53C895 and the low order
eight bits dene the register to be accessed. A decode of C_BE/ [3:0]
determines which registers and what type of access is to be performed.
PCI denes memory space as a contiguous 32-bit memory address that
is shared by all system resources, including the SYM53C895. Base
Address Register One determines which 256-byte memory area this
device occupies.
PCI denes I/O space as a contiguous 32-bit I/O address that is shared
by all system resources, including the SYM53C895. Base Address
Register Zero determines which 256-byte I/O area this device occupies.
3.2 PCI Bus Commands and Functions Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE/[3:0] lines
during the address phase. PCI bus command encoding and types appear
The I/O Read command reads data from an agent mapped in I/O
address space. All 32 address bits are decoded.
The I/O Write command writes data to an agent when mapped in I/O
address space. All 32 address bits are decoded.
The Memory Read, Memory Read Multiple, and Memory Read Line
commands read data from an agent mapped in memory address space.
All 32 address bits are decoded.