SCSI Registers
5-21
received in the middle of a data transfer, the SYM53C895
may transfer up to three additional bytes before halting to
synchronize between internal core cells. During
synchronous operation, the SYM53C895 transfers data
until there are no outstanding synchronous offsets. If the
SYM53C895 is receiving data, any data residing in the
DMA FIFO is sent to memory before halting.
When this bit is set, the SYM53C895 does not halt the
SCSI transfer when SATN/ or a parity error is received.
CON
Connected
4
This bit is automatically set any time the SYM53C895 is
connected to the SCSI bus as an initiator or as a target.
It is set after the SYM53C895 successfully completes
arbitration or when it has responded to a bus initiated
selection or reselection. This bit is also set after the chip
wins simple arbitration when operating in low-level mode.
When this bit is cleared, the SYM53C895 is not
connected to the SCSI bus.
The CPU can force a connected or disconnected
condition by setting or clearing this bit. This feature would
be used primarily during loopback mode.
RST
Assert SCSI RST/ Signal
3
Setting this bit asserts the SRST/ signal. The SRST/
output remains asserted until this bit is cleared. The
25
s minimum assertion time dened in the SCSI
specication must be timed out by the controlling
microprocessor or a SCRIPTS loop.
AESP
Assert Even SCSI Parity (force bad parity)
2
When this bit is set, the SYM53C895 asserts even parity.
It forces a SCSI parity error on each byte sent to the
SCSI bus from the SYM53C895. If parity checking is
enabled, then the SYM53C895 checks data received for
odd parity. This bit is used for diagnostic testing and
should be clear for normal operation. It can be used to
generate parity errors to test error handling functions.
IARB
Immediate Arbitration
1
Setting this bit causes the SCSI core to immediately
begin arbitration once a Bus Free phase is detected
following an expected SCSI disconnect. This bit is useful